The Signal Quality Analyzer MP1800A is a highly expandable, plug-in, modular-type, bit error rate tester (BERT). It incorporates a Pulse Pattern Generator (PPG) module for generating the highest-quality, highest-amplitude signals in the industry, as well as an Error Detector (ED) module with the highest input sensitivity available. The platform supports signal analyses, including Burst pattern, Bathtub Jitter and Eye Diagram measurements. Various types of jitter, such as SJ, RJ, BUJ, SSC, etc., can be generated using the built-in jitter modulation source, supporting device Jitter Tolerance tests.
The MP1800A BERT supports a wide range of bit rates from 0.1 to 32.1 Gbit/s for signal integrity analyses for various applications, such as 100 GbE (25Gx4), OTU-4 (28Gx4), 32G DP-QPSK, CEI-28G, 32G FC, Infiniband EDR (26G), etc. Additionally, combining the MP1800A with the MP1821A MUX and MP1822A DEMUX supports Bit Error Rate tests up to 56 Gbit/s, enabling easy upgrades to support next-generation applications, such as CEI-56G-VSR.
The number of channels per MP1800A-series PPG or ED module can be selected from 1ch, 2ch or 4ch, supporting multichannel synchronization for up to 8 channels at 32 Gbit/s. As a result, each channel of AOC, CFP, CXP, QSFP+, etc., modules can be measured simultaneously, enabling crosstalk and skew tolerance evaluation tests.
The SQA's PPG modules offer outputs up to 3.5 Vp-p, supporting the evaluation of modulators, such as EA and EML. In addition to generating IEEE and ITU-T burst and auxiliary signals for evaluating E-PON, G-PON, and 10GE-PON optical modules, the SQA's automated generation of burst data and auxiliary signal output timings shortens evaluation times and improves evaluation quality.
The ED module has a high sensitivity of just 10 mV as well as high-speed auto-adjustment of 1 second or less (auto-detects threshold level and phase point), supporting accurate and efficient measurement of low-output-amplitude devices, such as AOCs. Installing the Clock Recovery option enables stress jitter tolerance tests of SERDES with different Tx and Rx clocks and BER measurements of clock-less devices such as AOC in One box.
The J1621A and J1622A are Passive Linear Equalizers used to help remedy the impact of high frequency transmission line distortion. They can be connected to the ED in order to compensate PCB trace loss and improve EYE opening. In combination with High Sensitivity ED MU183040B/MU183041B, these equalizers enable BER and Jitter Tolerance testing of PHY devices with low EYE openings.
The Jitter Modulator generates wide-amplitude SJ up to 1 UI at a Jitter Frequency of 250 MHz, ensuring sufficient margin for receiver Jitter Tolerance tests. Additionally, the Intrinsic Jitter of 275 fs rms (nominal) is extremely low, not only when Jitter modulation is OFF but also when 0 UI is set at Jitter ON, ensuring accurate measurements even at low Jitter amplitudes. Moreover, as well as supporting RJ, BUJ, SSC, and Dual tone SJ, even the latest standards, such as CEI-28G, 100 GbE, etc., are supported too.
Anritsu’s MP1800A with Low-Intrinsic Jitter PPG, 4TAP Emphasis, High-Sensitivity ED, Equalizer for Eye Opening compensation, and automatic measurement software is the ideal total solution for Jitter Tolerance tests.
The MP1800A can be configured to generate the high quality, low S/N, 4 PAM and 8 PAM data signals required for the characterization of high-speed backplanes and 400 GbE interfaces using the 4 PAM/8 PAM Converter MZ1834A/MZ1838A. The bit error rates of three 4 PAM eye patterns can be measured simultaneously. The MP1800A is the ideal platform for accurate BER measurements of 4 PAM signals using the long-memory programmable pattern function and error-mask function for filtering out unwanted errors.