PCIe Express® (PCIe®)
Advance your R&D process efficiency
PCI Express® (PCIe®) is a high-speed serial interconnect standard that is widely used in data centers, computing platforms, storage systems, and automotive applications.
The PCIe specification is developed and maintained by the Peripheral Component Interconnect Special Interest Group (PCI-SIG®). Driven by growing demand for higher data throughput in AI servers and data centers, the latest PCIe 7.0 specification was released in 2025, and development of the next-generation PCIe 8.0 standard is already underway.
At the same time, increasing data rates have intensified challenges associated with electrical interconnects, including greater transmission losses and shorter achievable transmission distances. To address these limitations, the industry is actively advancing optical interconnect technologies that offer the potential for lower losses and faster data transmissions over longer distances than conventional electrical links.
PCI-SIG®, PCIe® and PCI Express® are registered trademarks of PCI-SIG.
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Add-In Card
Photonic wire
Connector
PCIe 7.0
PCIe 7.0 delivers a data rate of 128 GT/s, doubling the bandwidth of PCIe 6.0.
Optical interfaces are being considered to extend transmission reach.
White Paper:
Overcoming Design and Evaluation Challenges of Intra-Pair Skew in High-Speed Interfaces
The impact of intra-pair skew in differential signals, such as PCIe and USB, is becoming increasingly apparent in high-speed digital transmission.
This white paper discusses the effects of intra-pair skew, the associated technical challenges, and methods for evaluating skew.
White Paper:
PCIe® 6.0: Testing for a New Generation
PCI Express® (PCIe) 6.0 has increased the complexity of product design verification.
This White Paper outlines a variety of the technologies and suitable signal integrity measurement solutions.
PCIe Testing Challenges
In PCIe generations up to 5.0, Non-Return-to-Zero (NRZ) modulation was the mainstream approach, where each bit is transmitted using two voltage levels for digital data. However, to meet the demands for higher-speed and greater-capacity data transmission, PCIe 6.0 has adopted Pulse Amplitude Modulation 4 (PAM4), which uses four voltage levels to transmit two bits per symbol, as well as Forward Error Correction (FEC). These technologies continue to be used in PCIe 7.0. PAM4, a four-level modulation scheme, allows for double the bit rate compared to NRZ by transmitting two bits per symbol, thus improving bandwidth efficiency. On the other hand, PAM4 is more susceptible to jitter and noise, making their effects more pronounced. Consequently, the design of PCIe devices has become even more complex than before.
At every stage of development, from prototype debugging and design verification to compliance testing and commercial release, signal quality evaluation is essential for high-speed digital systems. Signal quality testing provides critical feedback for design improvements as well as enhances product reliability. Additionally, ensuring host–device interoperability requires physical layer testing, such as jitter tolerance assessments and Link Training evaluations during link establishment. Furthermore, in addition to normal cases, it is also required to verify the behavior in abnormal cases.
NRZ Waveform
PAM4 Waveform
PCIe Test Solutions in R&D
PCIe Testing both assures and improves the quality of digital signals of the PCIe device PHY layer.
Transmitter and Receiver Tests
The transmitter (Tx) test uses a Real-Time Oscilloscope (RTO) to evaluate the rise/fall times, amplitude, eye width, jitter, and more of the reference clock and data-signal output from the PCIe device. In addition, the Phase-Locked Loop (PLL) bandwidth is measured by the RTO using a Pulse Pattern Generator (PPG) as the signal source.
The receiver (Rx) test evaluates the PCIe device jitter tolerance, crosstalk, operating margin, and more by using a PPG and Bit Error Rate (BER) tester to impose stress, such as noise and jitter, on the electrical signals.
Anritsu’s Signal Quality Analyzer-R MP1900A is a high-performance, 8-slot modular BER tester. It supports physical layer measurements of high-speed bus interfaces, such as PCI Express, using NRZ/PAM4 signals—all in a single instrument.
Furthermore, Anritsu’s Sequence Editor function option 051 for the SI and PAM4 PPG provides a comprehensive solution for everything from constructing test patterns and sequences for high-speed digital interfaces to executing those tests, combining both efficiency and reliability. The Sequence Editor features an intuitive GUI, making it easy to construct sequences for normal, abnormal, and stress test scenarios. This enables flexible testing aligned with compliance requirements, as well as validation of physical layer performance, reproduction of logical layer fault behaviors, and efficient root cause analysis.
White Paper:
PCIe 6.0: Testing for a New Generation
Video:
MP1900A PCIe 6.0 Compliance Test
Leaflet:
Technical Note:
Empirical BER Characterization of Intra-Pair Skew for PCIe® at 64 GT/s
Application Note:
Protocol Test
In PCIe, link state transitions are managed by the physical layer’s Link Training and Status State Machine (LTSSM). Protocol testing verifies that the LTSSM transitions occur correctly. When a link failure occurs, the behavior of link training and LTSSM is analyzed to determine whether the root cause lies in the physical layer or the logical layer.
Transmitter tests, receiver tests, and protocol tests can all be performed by combining the Signal Quality Analyzer-R MP1900A, which integrates a PPG and BER tester, with a partner-provided RTO. Furthermore, by using dedicated software to automatically control both the MP1900A and the RTO, complex test conditions can be easily configured, contributing to shorter debugging and compliance testing times.
Brochure:
Signal Quality Analyzer-R MP1900A - PCIe/USB/Thunderbolt/Display Port Test Solutions
Interconnect Test
Debugging, such as characterizing causes of degraded signals in prototype devices under development, as well as improving performance, requires evaluating the insertion and return losses of parts and signal wires. This is called an interconnect test.
Anritsu's Vector Network Analyzers, such as the ME7838 series and MS4640B series, can evaluate the frequency characteristics, reflection characteristics (S-parameters), and impedance of electrical wiring in hardware, including printed circuit boards with USB devices or materials.
White Paper:
- PAM4 Demands Accurate S-Parameter
- Exploring VNAs: The Definitive Tool for Signal Integrity in High-Speed Digital Systems
Video:
Teledyne LeCroy × Anritsu
Anritsu offers PCIe test solutions in partnership with Teledyne LeCroy.
>>Learn More
Case Study
Qualitas Semiconductor Co., Ltd.
A leading company in high-speed interconnect IP development enhanced its verification capabilities and development efficiency by leveraging Anritsu’s vector network analyzer.
Micro-Star International Co., Ltd.
Overcoming the technical issues hindering high-speed digital transmission in the development of cutting-edge PCs and peripheral devices.
What has been achieved using a BER tester and VNA?
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