High-speed Interconnects and Backplanes
Hyperscale networks, cloud computing, and mobile Internet services – and the network traffic explosion created by them – are pushing data speeds to 100G and 200G, with 400G on virtually every roadmap. Assuring signal integrity (SI) at high data rates while minimizing cost is a major guideline when designing high-speed interconnects and backplanes incorporating the latest PCIe® , USB-C, Thunderbolt™, and other standards. Test solutions to effectively measure such complex high-speed designs must support measurements in the frequency and time domains to accurately determine SI.
Higher data rates introduce new design challenges for SI engineers when validating, debugging, and troubleshooting high-speed interconnects and backplanes. Accurate measurements need to be made on skin effects and dielectric loss on printed circuit boards (PCBs), as well as vias, stackups, and connector pins for engineers to have high design confidence.
As bit rates increase, the upper frequency limit of test instruments must rise for accurate evaluation of backplane and interconnect transmission characteristics. For example, higher speeds typically translate to higher test frequencies being required to perform measurements to the 3rd or 5th harmonic.
PAM4 Impact
Complex interconnect systems are now being developed using Pulse Amplitude Modulation 4-level (PAM4) to satisfy the high bandwidth demands. PAM4 can transmit twice as much data per symbol cycle as legacy Non-Return-to-Zero (NRZ) technology, making it better suited for current and emerging high-speed designs.
Among the trade-offs associated with PAM4 is that it adds signal complexity, as well as introduces potential nonlinearities. Jitter, noise, and crosstalk remain key concerns when measuring PAM4 signals. Test solutions must feature very clean clocks, robust clock recovery circuits, and sensitive symbol decoders/voltage slicers to measure PAM4 signals. Improved equalization schemes at the transmitter and receiver are necessary to address inter-symbol interference (ISI) caused by the channel, as well.
Testing High-speed Interconnects, Backplanes
Conventionally, two principal stimulus-response systems are used to characterize high-speed interconnects. Vector Network Analyzers (VNAs) measure S-parameters in the frequency domain while Time Domain Reflectometers (TDRs) measure impulse responses in the time domain.
To characterize high-speed interconnects, PCBs, backplanes, fixtures, and packages, SI engineers use broadband VNAs to conduct accurate and repeatable single-ended, balanced differential, and mixed-mode S-Parameter measurements. Making high quality S-parameter measurements in the frequency domain has some inherent advantages over time-domain-based instruments, notably dynamic range.
Network Extraction and De-embedding
Many channels used in high-speed designs have Baluns, connectors, PCB traces, and other fixtures that affect the measured S-parameters. To offset these factors, network extraction should be done. Network extraction is the process of determining the S-parameters for the features that need to de-embed from (or embed into) the measurement.
Frequency domain data alone, however, is not enough to verify performance. Advanced VNAs architectures support time domain measurements, as well. Such instruments can transform frequency data into the time domain to locate particular problems. To accurately convert the acquired signal into the time domain, the VNA needs extremely high resolution. By doing so, SI engineers can more accurately and efficiently locate discontinuities, impedance changes, and crosstalk issues.
While a VNA can be used as a single-instrument solution in SI design verification, it can also serve as a central instrument in a robust system that can include a bit error rate tester (BERT), oscilloscope, and other complementary tools. Complete systems test the quality of a signal transmission of single components or complete systems. The key in both applications is selecting the proper VNA for testing requirements.
