Webinar
400G Post FEC BER and Jitter Tolerance Test for Physical Layer Chip and Module
9/29/2022, 1:00 PM CT
High-speed and large-capacity transmission standards using PAM4 signaling, such as 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality. Consequently, jitter tolerance tests for SERDES, DSP, and CDR used by transceivers are required at both pre-FEC evaluations of bit error rate performance as well as at correctable/uncorrectable FEC symbol error performance.
