02/24/2026 - 02/26/2026 , Santa Clara Convention Center, Santa Clara, California
The Must Attend Event for Chip, Board, and Systems Design Engineers
DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
Experience the Future of High Speed Interconnect and Signal Integrity Testing
Join Anritsu to see how industry leading test and measurement solutions are enabling the next generation of high speed digital design. Visit Anritsu's booth #1143 to explore four live demo stations showcasing breakthrough innovations in 448G interconnect development, broadband S-parameter characterization, and advanced signal quality analysis—developed in collaboration with key industry partners.
448G Twinax Cable Development — VectorStar ME7838AX
In partnership with FIT, Anritsu demonstrates next generation 448G twinax cable development using the VectorStar ME7838AX 125 GHz broadband VNA, enabling high accuracy characterization of advanced high speed interconnects.
Automated Broadband S-Parameter Characterization — ShockLine VNA
This demo showcases how ShockLine VNA measurements combined with ATS driven automation and intelligent switch control enable efficient, end-to-end S-parameter characterization without repeated manual reconnections.
Signal Integrity & BER Analysis — MP1900A + LeCroy
See the Anritsu MP1900A Signal Quality Analyzer integrated with LeCroy instrumentation to deliver coordinated BER testing and signal integrity analysis for high speed serial interfaces.
High Performance BER Testing — Signal Quality Analyzer MP1900A
Explore the MP1900A Signal Quality Analyzer as a flexible, high performance solution for BER testing and signal quality validation, supporting R&D through production test environments.
Visit us at booth #1143
Technical Sessions:
A Scalable, Automated Approach to Signal Integrity Validation for High-Speed Interconnects
As high-speed interconnect technologies continue to scale for data center and AI applications, accurate and repeatable signal integrity characterization is increasingly critical. This presentation introduces a complete ShockLine signal integrity test solution built around the MS46524B Vector Network Analyzer, integrated with Anritsu’s ATS automation software and a scalable multiport RF switch box architecture.
Thursday February 26 | 9:00 AM – 9:45 AM
AI/DC pushing the boundaries of signal integrity, How difficult is it to test 224/448 Gbps electrical / optical interfaces to 145 GHz and beyond? Challenges and Solutions with Anritsu
AI/DC is really pushing the limits of electrical interfaces, high speed connectors and PCBs. The co-existance of Optical and electrical is not making life simpler for engineers developing next generation transceivers and electrical interfaces / backplanes etc.. The challenge is two ways, first on electrical side where E/E testing of TIA's, Driver amplifiers, and PCB backplanes is pushing the boundaries to 145 GHz RF bandwidth support and secondly, the Opto-electronics part (TOSA/ROSA/BOSA/COSA) where the two world of electronics and optics converge together to meet the ever increasing bandwidht requirement. In this world, the testing of discrete components, subassemblies and packaged devices where its either Electrical in- Optical out (E/O) or Optical in - electrical Out (OE) becomes a vital testing criteria for engineers. In this session we will cover all the aspects related to high speed testing wether its E/E, E/O, O/E , OO and Mutliport testing solution as well.
Thursday February 26 | 11:15 AM – 12:00 PM
PCI Express 7.0 Electrical Pathfinding Updates
PCI Express 7.0 has arrived! Served as high-bandwidth, low-latency, and keep track of the aggressive tradition of doubling I/O bandwidth every three years. PCI Express technology has continued to be a favorable option of interconnects that scales with the ever-expanding data demands. From AI/ML and high-performance computing applications, to hyperscale data centers. In this session, we will review PCI Express 7.0 transmitter and receiver tests per the official 1.0 Base Specification, highlighting measurement methodology updates from PCI Express 6.0, and share early study of how the key measurements extend their capability to expected CEM channels.
Thursday February 26 | 12:15 PM – 1:00 PM
Tx/Rx Validation and Compliance in a fraction of the time
This session will cover the latest test methods for High Speed Serial Serdes Tx, Rx, and Return Loss Compliance and Validation.
Examples will include standards such as USB4/Thunderbolt, DisplayPort 2.1, and PCI Express 6.0. For Transmitters, compliance automation as well as techniques for optimizing the use of oscilloscope equipment in the lab will be presented. For Receivers, Rx Calibration and BER/TER testing for NRZ, PAM3, and PAM4 signaling using the Anritsu MP1900A. Learn how to add Tx/Rx Return Loss, s-parameter measurements efficiently and cost effectively.
Thursday February 26 | 2:15 PM – 3:00 PM
PCIe 6.0 TX/RX LEQ Compliance Test
Hints and tips for passing the compliance test at the PCI workshop with the successful and repeatable stressed eye calibration. You will learn the Know How of the TX/RX LEQ test with the detailed block diagram and the test procedure. In addition, the presentation addresses how to troubleshoot when encountering the typical problems of TX/RX LEQ test and jitter tolerance test.
Thursday February 26 | 3:15 PM – 4:00 PM
Visit Anritsu at booth #1143
