Measuring 56 Gbit/s Band High-Speed Semiconductor Chips
Measuring 56 Gbit/s Band High-Speed Semiconductor Chips
56 Gbit/s BER Measurements
The bit rates of high-performance servers, switch backplanes, etc., are becoming increasingly faster while consuming less power. Evaluation of signal integrity is important for evaluating dropping input/output amplitudes of semiconductor chips such as SERDES and CDR to reduce power consumption. The signal output of these low-amplitude devices can be received securely using the high-sensitivity performance 25 mV (typ.) of the DEMUX MP1862A.
Jitter Tolerance Tests
Installing the Jitter Modulation Source MU181500B in the MP1800A supports independent and simultaneous injection of Dual SJ (two types), RJ, BUJ, and SSC jitter components for Jitter Tolerance tests meeting various standards, such as CEI-56G, etc.
Sinusoidal Jitter (SJ) |
Random Jitter (RJ) |
Bounded Uncorrelated Jitter (BUJ) |
Half Period Jitter (F/2 Jitter) |
Input Sensitivity Tests
With a wide tuning range of 0.5 Vp-p to 3.5 Vp-p max., the MUX MP1861A supports device input sensitivity tests (when 56 Gbit MP1861A-013 installed.) The MP1861A incorporates a 6-dB ATT as standard for use over a range of 0.25 Vp-p to 1.75 Vp-p. Anritsu recommends using a 6-dB ATT to prevent risk of damage from EOS (Electric Over Stress).
Bathtub Jitter Measurement
Standards such as CEI-56G specify device output Jitter Tolerance values. Bathtub Jitter measurement analyzes the device Total Jitter (TJ) and RJ and DJ components from changes in the bit error rate with phase. It also calculates the optimum bit error rate. A clean Clock reference signal is required by the DEMUX and ED at Bathtub Jitter measurement. The MP1862A supports Bathtub Jitter measurement using a clean Clock with jitter addition.
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