Multichannel Support, FEC Pattern Generation, ISI, and Error Count Import Functions
Anritsu Corporation (President Hirokazu Hamada) is starting sales of four PAM4 BERT options adding multichannel synchronization (max. 4ch/MP1900A main unit), multilane FEC*1 pattern generation for 400GbE*2, ISI*3 stressed signal generation simulating transmission path losses, and application software for capturing DUT error counts to the company’s Signal Quality Analyzer-R MP1900A. These options for the PAM4 PPG MU196020A released previously support bit error rate*4 tests of high-speed interfaces, such as 400GbE. This product is a hardware and software option for addition to the PAM4 PPG MU196020A. It adds 400-GbE PAM4*5 signal multilane, FEC pattern generation, and jitter addition functions, which are of increasing importance for transceivers and DSP*6 used by high-speed interfaces in data centers. These strengthened functions using only a PPG will help shorten customers' development and test times.
The spread of next-generation mobile communications and cloud applications is expected to greatly increase data communications traffic volumes. As a result, in addition to increasing speeds, communications infrastructure operators, such as data centers, are examining ways to expand transmission capacity using PAM4 and multilane technologies.
The future start of 400GbE in these data centers will require use of new transceivers supporting multilane technologies, such as QSFP-DD, and OSFP*7 as well as FEC in the PHY layer for PAM4 signal transmissions. Consequently, transceiver and device evaluations using a BERT must not only support previous jitter tolerance and input sensitivity measurements, but also key tests on the impact of crosstalk*8 due to use of multichannels, as well as error correction. In addition to adding multichannel and FEC pattern generation functions, the PAM4 PPG MU196020A also supports the required 400GbE transceiver PHY layer tests.
Moreover, to assure interconnectivity between interfaces defined by the 400GbE standards, chip-to-chip and chip-to-module transmission-path losses have been specified, causing time and cost issues due to the need to test ICs against multiple standards and to prototype multiple different PC boards*9 for testing the effects of transmission path losses. With PAM4 signaling, the gap between signal levels is only one-third that of the previous NRZ*10 technology, requiring tests under stricter conditions. As a result, the PAM4 PPG MU196020A has a built-in function for simulating signals after passage via a PC board—eliminating the need to prototype multiple PC boards to test transmission path losses—as well as an ISI function.
In addition, BER measurement of general high-speed devices is performed by receiving the output from the DUT at an error detector (ED) to measure bit errors. Conversely, at the early development stage, error measurements for specific test patterns, such as PRBS, use an error-check function built-into the DUT IC, which is convenient when no ED is available. At this stage, since PPG and DUT error measurement functions require various separate operations, users need unique designs, such as tracking operation when using the PPG and ED as a set for jitter tolerance*11 tests, as well as display of measurement results. Therefore, the MP1900A has a built-in function for communicating with the DUT IC error-check function, helping simplify MP1900A jitter tolerance measurements.
The Signal Quality Analyzer-R MP1900A is the market-leading bit error rate tester supporting generation of high-speed signals and signal analysis for 400G and faster speeds. These newly released options for the PAM4 PPG module add a multichannel function that can be expanded up to 4ch (per MP1900A main unit), a function for generating 100/200/400GbE FEC patterns and injecting errors, and an ISI function for simulating transmission path losses of various PC board designs at the PPG output port. As a result, these options support faster development and testing of 400GbE transceivers requiring multichannel measurements and error-correction tests using FEC.
Furthermore, the Error Counts Import function of the MP1900A application software can capture the DUT built-in error-check function measurement results for display on the MP1900A screen, facilitating IC error measurements, easy configuration of a jitter tolerance measurement system, and easy operation for efficient BER measurement at the initial IC development stage by purchasing only the PPG.
[Details of MP1900A PAM4 BERT here]
[Target Markets and Applications]
■ Target Markets: 400GbE transceivers and devices
■ Applications: Bit error rate evaluation of 400GbE transceivers and devices
Abbreviation for Forward Error Correction; one technology for controlling errors in data transmissions
Abbreviation for 400 Gigabit Ethernet; IEEE-defined communications standard
Abbreviation for Inter Symbol Interference; one type of signal distortion in serial transmissions causing degraded signals due to band limitations
*4 Bit Error Rate Test
Digital signal error rate test
Abbreviation for four-level Pulse Amplitude Modulation; a communications technology for controlling changes in voltage amplitude (pulse height). With PAM4, 2 bits of data are transferred using 4 levels in one time slot.
Abbreviation for Digital Signal Processor
*7 QSFP-DD, OSFP
Standards for 200GbE and 400GbE transceiver connectors
Leakage of one transmitted signal into another transmission path
*9 PC Board
Abbreviation for Printed Circuit Board (also printed substrate); a substrate for mounting and wiring electronic parts
Abbreviation for Non-Return-to-Zero; one technology for representing digital signals
*11 Jitter tolerance
One index of digital transmission quality expressing tolerance to jitter on the digital-signal time axis