5 June 2026 - ANRITSU CORPORATION announces a new CXL® (Compute Express Link®) 2.0/3.x test solution for CXL-enabled devices and memory evaluation which operates on Anritsu’s Signal Quality Analyzer-R MP1900A. This solution improves the efficiency of high-speed interface design and evaluation by enabling high-speed signal integrity evaluation for CXL.

Development Background
CXL is a next-generation interconnect technology enabling high-speed and efficient connections between CPUs, GPUs, and other accelerators, and memory and I/O devices. Semiconductor manufacturers are advancing development of CXL-compatible products. The standard continues to evolve, with CXL 2.0 based on PCIe Gen 5.0 and CXL 3.x based on PCIe Gen 6.0, expanding applications in ever-higher bandwidth environments.

The PCIe 5.0 transition from NRZ 32 Gbaud to PAM4 32 Gbaud for PCIe 6.0 significantly increases the complexity of signal quality evaluation. Likewise, CXL 3.x supports 64 GT/s transmission using PAM4 signalling, making it increasingly important to accurately and quickly distinguish physical-layer issues from those related to protocol behavior, even under abnormal and stress conditions.

Against this backdrop, there is a growing need for solutions to efficiently build test sequences not only for normal operation but also for abnormal and stress scenarios, while enabling consistently reproducible verification in multi-lane environments used to secure bandwidth. In addition, establishing an evaluation environment that helps identify issues from early development stages is increasingly important for improving design and evaluation efficiency and accelerating time-to-market.

Product Overview
Signal Quality Analyzer-R MP1900A
The MP1900A is a high-performance BERT (Bit Error Rate Tester) supporting a wide range of high-speed interfaces including PCIe, CXL, USB, Thunderbolt, DisplayPort, and 400 GbE/800 GbE. It features industry-leading high-quality PPG output, highly sensitive ED input, high-accuracy jitter sources (SJ, RJ, SSC, BUJ), and noise sources (CM-I/DM-I), and also supports Link Training functions and LTSSM analysis.

This solution helps users create and execute test sequences — including abnormal and stress tests in addition to normal scenarios defined in compliance testing — through intuitive GUI operation, helping accelerate verification while reducing evaluation rework. It also supports simultaneous evaluation of multiple lanes and realistic test conditions by reproducing scenarios, such as Jump and Loop. As a result, it contributes to isolating issues in high-speed signal integrity evaluation for CXL 2.0/3.x and improving overall interface quality.

*PCI Express® and PCIe® are registered trademarks of PCI-SIG. CXL® and Compute Express Link® are registered trademarks of Compute Express Link Consortium, Inc.

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