DesignCon – Anritsu Test Talks - August 18 in Room 210F
Join us for a full day of education and live demonstrations:
Title: Importance of Sequential Peeling Extraction and De-embedding When Designing PCBs
Abstract: Engineers designing and testing differential devices, particularly printed circuit boards (PCBs), rely on vector network analyzers (VNAs) as part of their continual quest to shorten design cycles and improve product time to market. As designs continue to extend to higher frequencies and board space is at a premium, certain VNA tools and test techniques gain importance. Learn more about sequential peeling extraction and de-embedding during this informative session.
Title: Open House for PCIe® 5.0 RX LEQ Test Live Demo (Walk in at any time)
Abstract: Anritsu will conduct live PCIe 5.0 LEQ test using a real G5 DUT. You will be able to see the test procedure of G5 LEQ test, using the Anritsu Signal Quality Analyzer-R MP1900A. Come in at any time to see this live demonstration!
Title: PAM4 BER and JTOL Test Solution for PCIe® 6.0 and Beyond
Abstract: This session will provide an overview of 32 Gbaud and above, PAM4 BER test and Jitter tolerance test. It will also include Forward Error Correction (FEC) and burst errors analysis. Who should attend: Engineers working on PCIe 6.0 or 400/800GE applications.
Title: Live Demo of PAM4 BERT and JTOL, FEC and Burst Error Analysis
Abstract: Please join this live demonstration of PAM4 JTOL test and FEC burst error analysis using Anritsu’s BERT Signal Quality Analyzer-R MP1900A.
The demo will show:
- PAM4 BERT Product Overview and Capabilities
- PAM4 BER and Jitter Tolerance Test
- FEC Burst Error Capture and Analysis
Title: Automotive Test Solutions
Abstract: This session will provide an overview of Anritsu test solutions for automotive, including 5G/cellular, infotainment / connectivity / Bluetooth® / WLAN, ADAS, RADAR, C-V2X and PCIe.
Title: USB Type-C® Standard PHY testing. What’s the same, and what’s different?
Abstract: Over the last few years, USB and DisplayPort have adopted Intel’s Thunderbolt PHY specification as a ‘building block’ for USB4™ and DisplayPort™ specifications at the physical layer. The highest data rates over the USB-C® are now 20Gb/s on each lane for data throughput of 40Gb/s on two lanes for USB4 and 80Gb/s over four lanes for DisplayPort 2.0. This session will discuss how the Compliance Test Specifications (CTS) and test methodologies are the same between these standards and how they differ as the industry’s paper test specifications get reduced to practice.
Title: PCIe 5.0 Receiver LEQ Compliance Test
Abstract: This session will provide an overview of the methods for solving some of the new test and measurement receiver challenges for PCIe® 5.0 at 32.0 GT/s.
You will learn:
- PCI-SIG® 5.0 compliance program
- Challenges and latest guidelines on 32 GT/s receiver testing from industry experts
- Nuances of the 32 GT/s stressed eye calibration and handling high loss backchannels with equalization
- Solving validation challenges with a receiver solution