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FAQ about Gain Chip

The following is a list of frequently asked questions (FAQ) about our Gain Chip.

Chip Configuration

Question

Is the active layer structure of the gain chip and BOA the same?

Answer

The active layer structure is basically the same, but there is a difference in the waveguide structure: the gain chip uses a bent waveguide structure, while the BOA uses an angled waveguide structure.

Question

Do the gain peaks and bandwidths match the ASE spectrum?

Answer

Basically, the gain peak and bandwidth are correlated with the ASE spectrum, but do not match exactly. The gain peak is usually located on the long wavelength side of the ASE peak.

Question

Does the gain chip for the C+L-band cover a wider bandwidth than for the C-band or L-band?

Answer

The C+L-band gain chip does not have a wide bandwidth, but the wavelength is adjusted to cover the region between the C-band and L-band.

Question

How high is the wall-plug efficiency?

Answer

The wall-plug efficiency, meaning the power conversion efficiency, is calculated from the current–optical output characteristic with external cavity resonance and therefore depends on the operating conditions. In our experimental example, it is estimated to be about 15%.

Question

How do the device characteristics change as the operating temperature increases?

Answer

As the temperature increases, the gain peak wavelength becomes longer and the gain decreases.

Question

What is the optical output exit angle?

Answer

It is about 20º to the perpendicular of the facet.

Configuration

Question

In addition to the sub-mount type, can you supply other types, such as bare chips?

Answer

Standard products are sub-mounted, and we can also consider TO packages, mounting on different carriers, and hermetically sealed packages to meet customers' requirements. Please contact us for details, including support for bare chips.

Application

Question

Is there a way to prevent mode hopping at wavelength sweeping?

Answer

The optical length of the chip can be adjusted by changing the current and chip temperature to suppress mode hopping.