Easily expandable and high-performance PPG and ED support Phy layer evaluations of high-speed interfaces

All-in-One Support for Evaluating Next-Generation NRZ/PAM4 Network Interfaces and High-Speed Serial Buses

The Signal Quality Analyzer–R MP1900A is a modular Bit Error Rate Tester (BERT) installing a pulse pattern generator (PPG) for outputting high-quality multi-channel NRZ/PAM4 signals over a wide bandwidth of 2.4 Gbit/s to 32.1 Gbit/s, a high-sensitivity input error detector (ED), Jitter modulation sources for Jitter Tolerance tests, etc.
Additionally, optional noise generation and 10Tap Emphasis functions can be installed for Voltage Noise Tolerance tests, etc., and installing the High-Speed Serial Data Test Software MX183000A software enables efficient design evaluation for increasingly faster PCIe, USB, and Thunderbolt receivers.

Easy Flexibility for Multi-Channel Measurements at Various Transmission Rates and Formats

The MP1900A series is an 8-slot modular instrument that can be easily customized by selecting and adding required function modules. This flexible expandability supporting the latest communications methods ensures both efficient R&D investment and the fastest time to market.

• 8 slots (per one MP1900A main unit)
• Maximum transmission capacity up to 512 Gbit/s supporting up to 16ch of NRZ (using 2ch PPG in all 8 slots)
• All-in-one support for both high-speed network interfaces and bus interfaces such as PCIe

Strengthened Signal Integrity Evaluations in Addition to New SI PPG, SI ED and Noise Generator Modules

The 10Tap Emphasis option installed in the transmission-side 21G/32 Gbit/s SI PPG MU195020A can accurately replay simulated waveforms for various devices and channels (corrected for loss after passage through channel) to help improve design efficiency.

• Bit rates of 2.4 Gbit/s to 32.1 Gbit/s
• 10Tap Emphasis
• Variable ISI function
• Multi-band CTLE (supports 8, 16, and 28 Gbit/s bands)
• Low Intrinsic Jitter data output 115 fs rms (typ.)
• High input sensitivity 15 mV (EYE Height) (typ.)
• NRZ/PAM4 support
• CDR SSC support
• Jitter (SJ/RJ/BUJ/SSC) and noise (CM/DM/White) tolerance measurements

Waveform adjustment using 10Tap Emphasis Function

Emphasis Setting Screen Example

The Variable ISI (option) can generate a signal with simulated Loss between the Tx and Rx channels of high-speed devices and can also easily output a Loss-corrected waveforms. As a result, channel-Loss dependent high-speed device performance tests can be run easily with good reproducibility, helping cut development time.

ISI Setting Screen Example

ISI, CEI-28G, 14 dB Loss waveform (typical)

Using the MP1900A series with the Jitter Modulation Source MU181500B, Jitter Tolerance Test MX183000A-PL001 software, and Noise Generator MU195050A for adding CM/DM/White Noise supports receiver tolerance tests in conformance with the various interface standards.

Sinusoidal Jitter (SJ)

Random Jitter (RJ)

Bounded Uncorrelated Jitter (BUJ)

Half Period Jitter (F/2 Jitter)

 

CM/DM Noise

White Noise

 

Low Intrinsic Jitter Data Output PPG

The MU195020A PPG has an Intrinsic Jitter of just 115 fs rms. As a result, it can generate PAM4 waveforms for wide Eye openings.

28.1 Gbit/s PRBS 231 – 1
Typical Output Waveform

Low intrinsic RJ 115 fs rms

28 Gbaud QPRBS13 Typical Output Waveform
(Output after G0375A remote head)

High-Sensitivity, Wideband Input ED

The assured ED input analog bandwidth is 40 GHz. This bandwidth supports evaluation of Eye margin characteristics with high reproducibility even at input of small signals.

Example of Eye Contour Measurement at Input of Small 50 mVp-p Signal

Bathtub Measurement Example

PCIe Link Training and LTSSM Analysis Function (MX183000A-PL021)

The explosive growth of data traffic due to the worldwide spread of smartphones and mobile terminals is accelerating adoption PCI Express Gen4 (16 GT/s) for communications equipment bus interfaces.
In addition, the faster PCI Express Gen5 (32 GT/s) standard is already being investigated as a means to increase speeds. Key issues are how to shorten design verification times for assuring signal integrity and how to hold-down infrastructure costs.
Interconnectivity between devices and equipment is an important subject in adoption of these high-speed serial interfaces, and troubleshooting whether a Link establishment fault is due to either a physical or logical cause is also important.
The MP1900A series PCI Express function has Protocol Awareness with a normal operation Link Training function for evaluating the PHY layer including Logical Sub-block plus an LTSSM (Link Training Status State Machine) analysis function for detecting abnormal state transitions. These all-in-one functions facilitate efficient PHY layer evaluation of PCIe Gen1 to Gen5 receivers through inspection and fault troubleshooting.

Supports physical layer measurements of add-in cards and system boards

• Tx/Rx Link Equalization Response Test
• Rx Link Equalization Test
• Receiver Jitter Tolerance Test

Link Training State transitions

LTSSM Log

The MX183000A-PL022 has a USB3.0/3.1 Link Training function as well as an analysis function for detecting LTSSSM state transitions to help troubleshoot causes of faults. Combined use with the Jitter Tolerance Measurement function (M183000A-PL001) supports consistent (or coherent) USB3.0/3.1 interface receiver tests.

Link to HSB page