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Generating High-Speed Serial BUS Link Sequences with Signal Quality Analyzer MP1800A


Anritsu Corporation (President Hirokazu Hashimoto) is starting sales on February 26 of its newly developed High-Speed Serial Data Test Software MX183000A application for generating PCI Express and USB Link sequence patterns and testing Jitter Tolerance using the company’s popular Signal Quality Analyzer MP1800A series.

Using this application software supports efficient design and verification with Link sequence to control device status and jitter load tests required for evaluating PCI Express and USB interfaces.

[Development Background]

The explosive increase in data communications traffic requires large increases in capacity and speed of digital communications systems. Increasing the speed of typical BUS interface standards, such as PCI Express*1 and USB*2, while assuring signal integrity is becoming more and more difficult and requires confirmation of margins using Jitter Tolerance tests*3.

High-speed BUS interfaces like PCI Express and USB require use of state machine control called LTSSM*4 to perform communications between devices, so measuring instruments performing device tests must also support LTSSM.

Using the High-Speed Serial Data Test Software MX183000A generates the pattern signals required by the state transition for transitioning to the loopback status required by Jitter Tolerance tests.

Furthermore, as well as supporting precision tolerance testing using PHY device Jitter Tolerance tests with impressed SJ/RJ/BUJ*5, measurement times are also shortened by verifying device margins using low-rate estimated BER measurements.

[Product Outline]

The High-Speed Serial Data Test Software MX183000A controls the MP1800A, Jitter Modulation Signal Source, Pulse Pattern Generator (PPG), and Error Detector (ED) to perform state machine control of the high-speed BUS interface and Jitter Tolerance tests, helping cut test man hours and assuring accurate signal integrity measurements.

[Features of High-Speed Serial Data Test Software MX183000A]

  • Jitter Tolerance Test Function (MX183000A Option-PL001)
    • Jitter Tolerance Test Function (MX183000A Option-PL001)
    • Verify device margin using low-rate estimated BER measurements
    • Output measurement result reports in HTML and CSV formats
  • Output measurement result reports in HTML and CSV formats
    • Control device status transition using sequence generation with support for PCI
      Express Base Specification Rev. 1.0-4.0 device Logical Sub Block evaluation
    • Generate 8B/10B, 128B/130B, Scramble, and SKIP Insertion
  • USB Link Sequence Generation Function (MX183000A Option-PL012)
    • Generate transition to Loopback mode for evaluating USB3.1 Gen. 1-2 devices
    • Generate 8B/10B, 128B/132B, Scramble, SKIP Insertion, and LFPS
[Details of MP1800A]


*1 PCI Express
Serial data bus standard defined by PCI-SIG and used mainly for internal PC communications; latest Gen. 4.0 standard supports bandwidth of 16 GT/s per lane.

*2 USB
Serial data bus standard defined by USB-IF and mainly used for peripheral devices connected to host device, such as PC; latest USB3.1 standard supports 10 Gbit/s.

*3 Jitter Tolerance
Test method for ascertaining serial data bus performance in which modulation data with variable Jitter input to receiver and defined as BER.

Abbreviation for Link Training and Status State Machine; state machine managing communications status between devices on serial data bus.

Abbreviations for Jitter types classified according to generation source and characteristics.
SJ: Sinusoidal Jitter
RJ: Random Jitter; wide and unbounded with width mimicking normal distribution.
BUJ: Bounded Uncorrelated Jitter; generated by external sources, such as crosstalk from adjacent signal lines.

For further information please contact:

Anritsu Pte Ltd
11, Chang Charn Road
#04-01 Shriro House
Singapore 159640
Tel : 65-62822400
Fax :65-62822533
Contact Us for more information.

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