PCI Express® Gen 5: Solving 32 GT/s Receiver Compliance and Validation Challenges
3/2/2021 , 2:00 PM EST
PCI Express® I/O bandwidth has doubled every 3 years on average, thereby leading to an increased demand for this full duplex, high-speed bus architecture. As the industry begins deploying the 5.0 revision, with a bit rate of 32 GT/s, new trends and guidelines emerge for receiver compliance and validation. This webinar will provide an overview of the methods for solving some of the new test and measurement receiver challenges for PCIe® 5.0 at 32.0 GT/s.
What you will learn:
- PCI-SIG® 5.0 compliance program
- Status of 5.0 specifications including Base, CEM, and the test specifications
- Challenges and latest guidelines on 32 GT/s receiver testing from industry experts
- Nuances of the 32 GT/s stressed eye calibration
- Handling high loss backchannels with equalization
- Thoughts on Rx testing with and without spread spectrum clocking (SSC)
- Solving validation challenges with a receiver solution from Anritsu & Tektronix
Hiroshi Goto, Senior Market Development Manager, Anritsu
Hiroshi Goto has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions, including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager. Mr. Goto holds a Bachelor’s degree in Physics from Aoyama Gakuin University. He resides in the Dallas area and has authored numerous industry application notes and white papers and frequently speaks on the topic of signal integrity.
David Bouse, Systems Engineer for PCI Express Solutions, Tektronix
David Bouse joined Tektronix as the PCI Express Systems Engineer in December 2018. David is very active within the PCI-SIG EWG, CEM, & SEG workgroups with a recent focus on 64 GT/s Tx SNDR measurements methodologies and reference clock high frequency jitter measurements for the 5.0 standards. Previously he was working on USB & PCIe Industry enabling with a focus on Tx/Rx Test methodologies, Waveform Post-Processing tools (SigTest), Test Fixture design, and test specification development.