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DesignCon 2019

1/30/2019 - 1/31/2019 , Santa Clara, CA

Anritsu Booth #615 Demonstrations

  • 400G Optical Chip/Module
  • 200/400G PAM4 BER and Jitter Tolerance
  • PCIe G3/G4/G5 Receiver Compliance
  • High Speed Serial Bus Automated Receiver (PCIe, USB, TBT, 400GE)
  • 43.5 GHz 4-Port VNA Signal Integrity
  • 25/100Gbase-r Active Optical Cable Verification
  • 70/110 GHz 4-Port VNA Signal Integrity

Anritsu Complimentary Training and Workshops
(Thursday January 31, 2019 held in the Santa Clara Convention Center, Great America Room 2)

Time

Presentations

Topic

Speaker(s)

Outlook Link

10:05 am - 10:45 am

Available after event

PCIe G3/G4 TX/RX
Compliance Test and Ready for 5G

Patrick Connally
(Teledyne LeCroy)

11:05 am - 11:45 am

Available after event

PCIe G4 TX/RX LEQ and JTOL Test
Live Demo and How to Troubleshoot

Hiroshi Goto
(Anritsu)

2:00 pm - 2:40 pm

Available after event

400G PAM4 BER Test Solution
(IEEE, OIF/CEI, IBTA)
64Gbaud PAM4 Generation,
32Gbaud PAM4 BER and JTOL Test

Hiroshi Goto
(Anritsu)

2:50 pm - 3:30 pm

Available after event

32Gbaud PAM4 BER and JTOL test
Live Demo (64Gbps per Lane)

James Morgante
(Anritsu)



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