Skip to main content

DesignCon 2018

1/31/2018 - 2/1/2018 , Santa Clara, CA

Visit Anritsu Booth #741 at DesignCon!

Solution Demonstrations Include:

  • 200/400G PAM4 BER
    (IEEE 802.3, CEI, IBTA)
  • 100G AOC Jitter Tolerance
  • All-in-one Portable 25Gbase / 100Gbase-CR4/KR4 Bit Error Rate + RS-FEC Test Solution
  • High-Speed Serial Bus Receiver
    (PCIe 4.0, Thunderbolt™, USB 3.0)
  • PCIe 4.0 Receiver Compliance
  • 70 GHz 4-Port VNA Signal Integrity
  • 43.5 GHz 4-Port VNA Signal Integrity
  • Automated VNA SI Compliance

Don’t Miss our Technical Sessions!

Hear industry experts present on the latest in testing solutions on Thursday, February 1 in Great America Meeting Room 2.


Thursday, February 1, 2018

Time

Topic

Speaker(s)

Outlook Link

10:15 a.m. - 10:55 a.m

200/400G PAM4 BER Test Solution (IEEE 802.3, CEI, IBTA)

Hiroshi Goto (Anritsu)

11:05 a.m. - 11:45 a.m

56G PAM4 BER Test Live Demo

James Morgante (Anritsu)

2:00 p.m. - 2:40 p.m

PCI EXPRESS GEN3, GEN4 AND GEN5 PHYSICAL LAYER TEST REQUIREMENTS AND PROCEDURES

Patrick Connally (Teledyne LeCroy)

2:50 p.m. - 3:30 p.m

High Speed Serial Bus Receiver Test Solution (PCIe Gen4, Thunderbolt, USB 3.0)

Mike Engbretson (Granite River Labs)




DesignCon 2018