Anritsu Corporation (President Hirokazu Hamada) is demonstrating its world-beating PAM4*1 Error Detector (ED) supporting Bit Error Rate Tests*2 at transmission rates up to 116 Gbit/s at the CIOE 2019 (China International Optoelectronic Exposition held in Shenzhen, China, from September 4 to 7) and at the ECOC Exhibition 2019 (held in Dublin, Ireland, from September 23 to 25).
With the world’s highest operation bit rate and Rx sensitivity, this new ED module for Anritsu’s popular Signal Quality Analyzer-R MP1900A Series PAM4 BERT supports high-accuracy BER measurement of PAM4 signals when combined with the previously released PAM4 Pattern Signal Generator.
Communications data traffic volumes are expected to grow with the spread of next-generation 5G mobile communications and Cloud computing services. As a result, data centers supporting fast, large-capacity communications are examining speed increases to 400GbE*3 using four 53.125-Gbaud PAM4 lanes as well as future upgrades to 800GbE*4 using eight PAM4 lanes.
Since the PAM4 method expresses 2 bits of data with four amplitude levels, it has one-third the signal level difference of the NRZ*5 method using two levels, requiring instruments for evaluating signal quality (integrity) to have much higher input sensitivity performance than previously. Moreover, in addition to faster speeds, it is no longer possible to ignore the effect of losses from components such as PC boards, cables, connectors, etc., in the transmission path on measured results. As a result, evaluating the true performance of the measurement target demands not only excellent fundamental performance such as sensitivity and frequency bandwidth, but also solutions offering high-level integrated functions, such as Clock Recovery*6 and an Equalizer*7, to compensate for the impact of loss.
Anritsu developed this ED with built-in clock recovery and equalizer functions to implement world-beating high-sensitivity performance for PAM4 BER measurements.
The Signal Quality Analyzer-R MP1900A Series PAM4 BERT is the market-leading Bit Error Rate Tester for communications speeds at 400G and above, and supports high-level signal generation and analysis.
The demonstrated PAM4 ED module uses a unique InP*8 semiconductor Rx circuit to achieve a sensitivity performance of 50 mV (typ.) for a 58-baud PAM4 input. Additionally, the built-in clock recovery and equalizer functions, high sensitivity at upper operating frequency, and transmission path compensation, support never-before-seen validation of BER measurement results. As a result, the true performance of optical transceiver modules and devices, as well as specification margins, can now be evaluated accurately.
[Click here for details of available MP1900A PAM4 BERT products.]
[Target Markets and Applications]
- Target Markets: Manufacturers of 400GbE communications equipment and devices
- Applications: Bit Error Rate evaluations of 400GbE communications equipment and devices
Transmission method using voltage amplitude control (pulse height) sending 2 bits of data as four levels in each time slot
*2 Bit Error Rate Test
Digital signal error rate test
*3 and *4 400GbE and 800GbE
IEEE-defined communications test standards
Abbreviation for Non-Return-to-Zero; one method for representing a digital signal
*6 Clock Recovery
Technology used by digital transmissions for extracting Clock from received Data signal with superimposed Clock
Signal-conditioning (adjustment) technology used at data transmission for optimizing frequency characteristics of transmitted signal
Indium phosphide compound semiconductor
For further information please contact:
Anritsu Pte Ltd
11, Chang Charn Road
#04-01 Shriro House
Tel : 65-62822400
Contact Us for more information.