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56G/64G bit/s MUX MP1861A

56G/64G bit/s MUX

MP1861A
This product has been discontinued
Overview
  • 56G/64G bit/s Wide Bandwidth: CEI-56G, 400 GbE, FEC Bit Rate
  • 2:1 MUX, 1:2 DEMUX: Expand 28G/32G 2ch BERT to 56G/64G
  • Compact Remote Head: Reduces DUT connection cable losses
  • Excellent Signal Quality and Rx Sensitivity: High-accuracy measurements of
    semiconductor chip
    • Intrinsic random jitter 200 fs rms (typ.)
    • Max. variable amplitude output: 3.5 Vp-p
    • Input sensitivity: 25 mV (typ.), single-end, eye height
  • Versatile Signal Integrity Measurement Functions:  Supports CEI-56G, 400 GbE tests
    • TJ/DJ/RJ/Bathtub Jitter, Eye Diagram, Eye Margin Auto-measurements
    • Jitter tolerance tests (using MU181500B)
        • Supports generation of SJ, RJ, BUJ, SSC, Dual Tone SJ, Half Period Jitter (Even/Odd Jitter)
        • SJ generation with large amount: 0.55 UI @ fm 250 MHz
    • Crosstalk tests and Skew tolerance using variable data skew by using multi-channel
  • High Expandability
    • Sync pattern generation and BER measurements for up to four channels simultaneously
    • Emphasis signal generation (using MZ1854A, MP1861A 2ch sync, 57.8 Gbit/s)
    • PAM4 signal generation (using MZ1854A, MP1861A 2ch sync, 56.2 Gbit/s)
  • Supports burst signal test
  • Max. 512 Mbit/ch programmable data pattern
  • Auto PPG-to-MUX phase adjustment at bit rate change using auto-alignment function

Traffic volumes at data centers are exploding with the spread of cloud computing services. To solve this problem, new high-speed interfaces, such as 400 GbE and CEI-56G, are being explored to speed up communications between servers and network equipment. The receiver characteristics and jitter tolerance are key performance indicators of PHY devices, such as SERDES, used by these high-speed interfaces. Combining the 56G/64G bit/s MUX MP1861A and 56G/64G bit/s DEMUX MP1862A with an MP1800A with installed PPG, ED and jitter modulation source supports generation of serial NRZ data up to 64 Gbit/s, as well as BER and jitter tolerance measurements. The tolerance to various jitter components, such as SJ, RJ, BUJ, SSC, Dual Tone SJ, Half Period Jitter (Even/Odd Jitter), can be measured along with Bathtub Jitter to support new standards, such as CEI-56G.

■ 56G/64G bit/s MUX MP1861A

Item Specifications
Data Output Bit Rate 8 Gbit/s to 56.2 Gbit/s
8 Gbit/s to 64.2 Gbit/s (MP1861A-001)
No. of Channels 1ch and parallel sync up to 4ch by connecting MP1800A
Amplitude 0.5 Vp-p to 2.5 Vp-p (≤56.2 Gbit/s, MP1861A-011)
1.0 Vp-p to 2.5 Vp-p (>56.2 Gbit/s, MP1861A-011)
0.5 Vp-p to 3.5 Vp-p (≤56.2 Gbit/s, MP1861A-013)
1.0 Vp-p to 3.5 Vp-p (>56.2 Gbit/s, MP1861A-013)
Intrinsic Random Jitter*1 200 fs rms (typ.)
Half Period Jitter ±20 Steps
Dimensions and Mass 120 (W) × 90.9 (H) × 140 (D) mm (excluding projections); ≤5 kg
28G/32G bit/s PPG MU183020A/21A
      +
28G/32G bit/s ED MU183040B/41B
      +
56G/64G bit/s MUX MP1861A
      +
56G/64G bit/s DEMUX MP1862A
System Jitter Tolerance
  Typical example at 56.2 Gbit/s
System Jitter Tolerance

*1: Using sampling oscilloscope with intrinsic jitter of <200 fs rms, excluding sampling oscilloscope characteristic intrinsic jitter
Library
VIDEOS
How to Prevent ESD and EOS Damaging Measuring Instruments and DUT

How to Prevent ESD and EOS Damaging Measuring Instruments and DUT
Learn the necessary steps to prevent ESD/EOS damage to your DUT and your measuring instrument.

MP1861A/62A 56G/64G bit/s MUX/DEMUX

Introducing 64G MUX/DEMUX Modules for MP1800A BERT
Anritsu's new MP1861A 56/64 Gbit/s MUX and MP1862A 56/64 Gbit/s DEMUX modules for the MP1800A BERT Signal Quality Analyzer.