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56G/64G bit/s MUX MP1861A

56G/64G bit/s MUX

This product has been discontinued
  • 56G/64 Gbit/s Wide Bandwidth:  CEI-56G, 400 GbE, FEC Bit Rate
  • 2:1 MUX, 1:2 DEMUX:  Expand 28G/32G 2ch BERT to 56G/64G
  • Compact Remote Head:  Reduces DUT Connection Cable Losses
  • Excellent Signal Quality and Rx Sensitivity:  High-accuracy Measurements of Semiconductor Chip
    • Intrinsic Random Jitter 200 fs rms (typ.)
    • Max. Variable Amplitude Output: 3.5 Vp-p
    • Input Sensitivity: 25 mV (typ.), Single-end, Eye height
  • Versatile Signal Integrity Measurement Functions:  Supports CEI-56G, 400 GbE Tests
    • TJ/DJ/RJ/Bathtub Jitter, Eye Diagram, Eye Margin Auto-measurements
    • Jitter Tolerance Tests (using MU181500B)
        • Supports SJ, RJ, BUJ, SSC, Dual Tone SJ, Half Period Jitter (Even/Odd Jitter)
        • SJ Generation with large amount: 0.55 UI @ fm 250 MHz
    • Crosstalk Tests using Variable Data Skew by using multi-channel
  • High Expandability
    • Sync Pattern Generation and BER Measurements for up to 4 Channels Simultaneously
    • Emphasis Signal Generation (using MZ1854A, MP1861A 2ch Sync, 57.8 Gbit/s)
    • PAM4 Signal Generation (using MZ1854A, MP1861A 2ch Sync, 56.2 Gbit/s)
    • Supports Burst Signal Test
    • Max. 512 Mbit/ch Programmable Data Pattern
    • Auto PPG-to-MUX Phase Adjustment at Bit Rate Change using Auto-Alignment Function

Traffic volumes at data centers are exploding with the spread of cloud computing services. To solve this problem, new high-speed interfaces, such as 400 GbE and CEI-56G, are being explored to speed-up communications between servers and network equipments. The receiver characteristics and Jitter Tolerance are key performance indices of PHY devices, such as SERDES, used by these high-speed interfaces. Combining the 56G/64G bit/s MUX MP1861A and 56G/64G bit/s DEMUX MP1862A with an MP1800A with installed PPG, ED, and Jitter modulation source supports generation of serial NRZ data up to 64 Gbit/s, as well as BER and Jitter Tolerance measurements. The tolerance to various Jitter components, such as SJ, RJ, BUJ, SSC, Dual Tone SJ, Half Period Jitter (Even/Odd Jitter), can be measured along with Bathtub Jitter to support new standards, such as CEI-56G.

■ 56G/64Gbit/s MUX MP1861A

Item Specification
Data Output Bit Rate 8 Gbit/s to 56.2 Gbit/s
8 Gbit/s to 64.2 Gbit/s (MP1861A-001)
No. of Channels 1ch and parallel sync up to 4ch by connecting MP1800A
Amplitude 0.5 Vp-p to 2.5 Vp-p (≤56.2 Gbit/s, MP1861A-011)
1.0 Vp-p to 2.5 Vp-p (>56.2 Gbit/s, MP1861A-011)
0.5 Vp-p to 3.5 Vp-p (≤56.2 Gbit/s, MP1861A-013)
1.0 Vp-p to 3.5 Vp-p (>56.2 Gbit/s, MP1861A-013)
Intrinsic Random Jitter*1 200 fs rms (typ.)
Half Period Jitter ±20 Steps
Dimensions and Mass 120 (W) × 90.9 (H) × 140 (D) mm (excluding projections), ≤5 kg
28G/32G bit/s PPG MU183020A/21A
28G/32G bit/s ED MU183040B/41B
56G/64G bit/s MUX MP1861A
56G/64G bit/s DEMUX MP1862A
System Jitter Tolerance
  Typical example at 56.2 Gbit/s
System Jitter Tolerance

*1: Using sampling oscilloscope with Intrinsic Jitter of <200 fs rms, excluding sampling oscilloscope characteristic intrinsic jitter
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